(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improved etching in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the prior art, there are many problems which relate to thickness loss or damage to the various silicon oxide layers used in a large scale integration semiconductor process of today. For example, the isolation oxide layer on polysilicon layers sustains substantial damage during conventional plasma etching steps. Further, there is poor endpoint detection stability and repeatability of lightly doped drain (LDD) spacer and isolation layer plasma etch process. There is poor silicon oxide thickness control of LDD spacer and isolation layer plasma etch process. Also, there is poor stability of oxide removal process on capacitor polysilicon area. The isolation oxide layer may be damaged on self-aligned contact plasma etch.
Other workers in the field have encountered the above problems. U.S. Pat. No. 4,963,502 attempts to overcome similar, but different problems using silicon nitride spacer and caps over their polysilicon gate structure. U.S. Pat. No. 4,988,643 M. H. Tsou shows the use of silicon nitride cap over the polysilicon gate material to prevent oxidation of the gate electrode.